sdram controller

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Beuler? Beuler?

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??? Beuler ???

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Ferris Beuler's Day Out? Anyone? Anyone? Shows my age I suppose :-)

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I didn't see that film (yet) but a quick peek at Wikipedia didn't give me a clue what the connection is. Neither (IMHO) does the urban dictionary's definition (http://www.urbandictionary.com/define.php?term=beuler) apply.

Now back to your question:

I guess a lot of people have written their own controller. I have done a few, am in the process of doing another one but contemplating to just use Altera's IP and focus on other challenges in our products.

PCB layout: you do not have to take any more care for PLL signals as for other output signals; evidently they all have the same range of rise time. Of course a clock signal over a poorly laid out PCB track shows it self ...

Running the DRAM refresh from the video access is something I already did back in 1983 - building the controller with PALs and delay lines, saving a few expensive PALs and real estate. It simplifies the controller considerably.

I actually misspelled it. It's bueller. My bad :-)

The z80 had a DRAM refresh counter which I've used before but with SDRAM things seems to be a bit more complicated. Since this will be my first (simple) controller I'll probably base things around video timing with refresh taking place at fixed intervals, done in batches ( i.e. refreshing 4 rows each line or something similar ).

-Mux

Alright, after having perused various datasheets, I have a (perhaps) obvious question with regards to clocking and latency. Let me see if I can phrase this correctly:

Given a certain clock frequency, you can calculate how many clocks you'd need in order to satisfy timing requirements. For example, a tRCD of 15ns at 100mhz would imply 2 clocks, which would give you 20ns and therefore meet the timing requirements, whereas a 200mhz clock would imply at least 3 clocks. These figures are all listed in the datasheets as well as the timing in nanoseconds.

My question is whether or not SDRAM needs to be clocked or if you just need to satisfy those timing requirements. In the example above, you could either wait two clock periods or, if you would lower the clock speed (I know, different discussion) to say, 25mhz, you could submit two commands back-to-back as there would be ample time to satisfy the timing requirements.

So I guess to sum it up, are commands and data (in/out) the only ones that need to be clocked or do you NEED to clock in NOPs as SDRAM is a synchronous, pipelined architecture?

-Mux

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Alright, after having perused various datasheets, I have a (perhaps) obvious question with regards to clocking and latency. Let me see if I can phrase this correctly:

Given a certain clock frequency, you can calculate how many clocks you'd need in order to satisfy timing requirements. For example, a tRCD of 15ns at 100mhz would imply 2 clocks, which would give you 20ns and therefore meet the timing requirements, whereas a 200mhz clock would imply at least 3 clocks. These figures are all listed in the datasheets as well as the timing in nanoseconds.

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My question is whether or not SDRAM needs to be clocked or if you just need to satisfy those timing requirements. In the example above, you could either wait two clock periods or, if you would lower the clock speed (I know, different discussion) to say, 25mhz, you could submit two commands back-to-back as there would be ample time to satisfy the timing requirements.

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Being SDRAM with the 'S for Synchronous' clocking is quite elementary ...

The Cas-latency is specified in clocks and is minimum two (2).

In theory at very low frequnecies this easily could be lowered to one (1) but I guess that the manufacturers (primarily JEDEC) didn't see the use of this so it can not be specified either.

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So I guess to sum it up, are commands and data (in/out) the only ones that need to be clocked or do you NEED to clock in NOPs as SDRAM is a synchronous, pipelined architecture?

-Mux

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Yes you clock in NOPs, but this is automatic as a NOP is the absence of any other command.

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In theory at very low frequencies this easily could be lowered to one (1) but I guess that the manufacturers (primarily JEDEC) didn't see the use of this so it can not be specified either.

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Yeah, I get that. My question though is whether or not wait-states need to be synchronous (ie clocked in) as well or if you just need to satisfy the timing requirement. So while the diagrams show (on average) 8-10 clocks at 100mhz, about 4-5 of those clocks are nops. At a lower frequency, you'd satisfy the timing constraints with fewer clocks, thereby (roughly) getting the same performance.

I'll give it a whirl. It'd save me a PLL which would allow me to go with a cheaper FPGA..

-Mux

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My question though is whether or not wait-states need to be synchronous (ie clocked in) as well or if you just need to satisfy the timing requirement. So while the diagrams show (on average) 8-10 clocks at 100mhz, about 4-5 of those clocks are nops. At a lower frequency, you'd satisfy the timing constraints with fewer clocks, thereby (roughly) getting the same performance.

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As you say most timings are in ns, so at a lower frequency you need less clocks to satisfy that. Unfortunately the Cas-latency is specified in clocks.

And yes all 'waitstates' have to be clocked as NOPs, but again NOPs come free.

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I'll give it a whirl. It'd save me a PLL which would allow me to go with a cheaper FPGA..

-Mux

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Depends on how many you are going to produce. In a one-off project, I once made the mistake to stay with a smaller device. If I had upgraded to the next size even at twice the cost I would have finished on time ...

IMHO, you don't need a PLL to interface to an SDR SDRAM

Thanks Josyb!

Alright, that's kinda what I thought. Commands and CAS-latency need to be clocked but the mandatory waiting time does not. In that case, at 25mhz it looks I can issue an activate followed by a read in the next clock. Then that needs to be followed up with 2 CAS-latency clocks to get the data moved through the pipeline.

Awesome! Thanks again!

-Mux