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My question though is whether or not wait-states need to be synchronous (ie clocked in) as well or if you just need to satisfy the timing requirement. So while the diagrams show (on average) 8-10 clocks at 100mhz, about 4-5 of those clocks are nops. At a lower frequency, you'd satisfy the timing constraints with fewer clocks, thereby (roughly) getting the same performance.
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As you say most timings are in ns, so at a lower frequency you need less clocks to satisfy that. Unfortunately the Cas-latency is specified in clocks.
And yes all 'waitstates' have to be clocked as NOPs, but again NOPs come free.
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I'll give it a whirl. It'd save me a PLL which would allow me to go with a cheaper FPGA..
-Mux
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Depends on how many you are going to produce. In a one-off project, I once made the mistake to stay with a smaller device. If I had upgraded to the next size even at twice the cost I would have finished on time ...
IMHO, you don't need a PLL to interface to an SDR SDRAM
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