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In theory at very low frequencies this easily could be lowered to one (1) but I guess that the manufacturers (primarily JEDEC) didn't see the use of this so it can not be specified either.
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Yeah, I get that. My question though is whether or not wait-states need to be synchronous (ie clocked in) as well or if you just need to satisfy the timing requirement. So while the diagrams show (on average) 8-10 clocks at 100mhz, about 4-5 of those clocks are nops. At a lower frequency, you'd satisfy the timing constraints with fewer clocks, thereby (roughly) getting the same performance.
I'll give it a whirl. It'd save me a PLL which would allow me to go with a cheaper FPGA..
-Mux
Honored Contributor
