Honored ContributorI have created a project by loading SCFIFO megafunction generated vhdl file. When I am simulating in MODELSIM, OUTPUT DATA is not coming even when the Read pulse is enabled. Someone kindly help.
Honored ContributorCheck for any warning messages on the ModelSim console (transcript).
Did you add the 'altera_mf' library to your ModelSim simulation?Honored ContributorYeah I have added the library. I am simulating .vhd file which is generated after megafunction configuration. Problem is during simulation WRITE operation is working fine for every clock. But read operation is not working when RD signal is enabled. Kindly post if you have a working SCFIFO code. I ll try to simulate that and check mine. By the way code is uploaded. If possible can you verify it.
Honored ContributorI posted simulation files in this thread a while ago:
http://www.alteraforum.com/forum/showthread.php?t=38988 Cheers, DaveHonored ContributorI bet the SCFIFO is working just fine. Its your app code thats not working.
Instead of blaming the SCFIFO thats used in 1000s of projects worldwide without a problem, why not post your interface code and maybe we can help with that.Honored Contributori have linked it in my first message.
Honored Contributorcan you attach the file again.
Honored ContributorThats not your logic - thats the SCFIFO generated from the megawizard.
Honored ContributorCan't I simulate the same which is generated.
Honored ContributorWith the configuration of the FIFO you chose it will take one clock cycle after a 'rdreq' pulse for the data to show up on the output. Does your simulation code account for this?
Can you post your testbench code so that we can see what you are doing with the FIFO?Honored ContributorHere I have attached. Its not a testbench code.
