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Altera_Forum's avatar
Altera_Forum
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12 years ago

SCFIFO megafunction not working!!

I have created a project by loading SCFIFO megafunction generated vhdl file. When I am simulating in MODELSIM, OUTPUT DATA is not coming even when the Read pulse is enabled. Someone kindly help.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

With the configuration of the FIFO you chose it will take one clock cycle after a 'rdreq' pulse for the data to show up on the output. Does your simulation code account for this?

Can you post your testbench code so that we can see what you are doing with the FIFO?