Forum Discussion
Altera_Forum
Honored Contributor
12 years agoYeah I have added the library. I am simulating .vhd file which is generated after megafunction configuration. Problem is during simulation WRITE operation is working fine for every clock. But read operation is not working when RD signal is enabled. Kindly post if you have a working SCFIFO code. I ll try to simulate that and check mine. By the way code is uploaded. If possible can you verify it.