Same PLL clock domain crossing

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... signals from the 100Mhz are long enough ...

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I guess you meant 80MHz here.

In this case no special constraints are required, since the clocks have a simple setup/hold relationship.

You possibly may want to add multicycles if you don't need the strict default relationship

Sorry I meant the 80Mhz

Thank you.

The main purpose for this is that I want to take one data from the fast domain, drop the next, and so on. Take one and leave one.

In fact you indeed _need_ constraints, but the good news is that you get the constraints you need by simply using the Altera extension to SDC "derive_pll_clocks".

Make sure you do not place the two clocks in different clock groups nor cut the timing paths.

Timequest will report the clock to clock transfers.

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In fact you indeed _need_ constraints, but the good news is that you get the constraints you need by simply using the Altera extension to SDC "derive_pll_clocks".

Make sure you do not place the two clocks in different clock groups nor cut the timing paths.

Timequest will report the clock to clock transfers.

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OK I use derive_pll_clocks as you suggest.

The design is very simple so I don't use clock groups.

Thanks