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Altera_Forum
Honored Contributor
Honored ContributorSame PLL clock domain crossing
I have two clock outputs from one PLL. One clock is 80Mhz and the other is 40Mhz. Valid and data signals from the 100Mhz are long enough in time to be seen in the 40Mhz domain. My question is, s...
Altera_ForumHonored Contributor
Honored ContributorSorry I meant the 80Mhz
Thank you. The main purpose for this is that I want to take one data from the fast domain, drop the next, and so on. Take one and leave one.
