Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSame PLL clock domain crossing
I have two clock outputs from one PLL. One clock is 80Mhz and the other is 40Mhz. Valid and data signals from the 100Mhz are long enough in time to be seen in the 40Mhz domain. My question is, s...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- ... signals from the 100Mhz are long enough ... --- Quote End --- I guess you meant 80MHz here. In this case no special constraints are required, since the clocks have a simple setup/hold relationship. You possibly may want to add multicycles if you don't need the strict default relationship
