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Altera_Forum's avatar
Altera_Forum
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9 years ago

Same PLL clock domain crossing

I have two clock outputs from one PLL. One clock is 80Mhz and the other is 40Mhz. Valid and data signals from the 100Mhz are long enough in time to be seen in the 40Mhz domain. My question is, s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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... signals from the 100Mhz are long enough ...

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I guess you meant 80MHz here.

In this case no special constraints are required, since the clocks have a simple setup/hold relationship.

You possibly may want to add multicycles if you don't need the strict default relationship