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Honored Contributor
Honored ContributorSame PLL clock domain crossing
I have two clock outputs from one PLL. One clock is 80Mhz and the other is 40Mhz. Valid and data signals from the 100Mhz are long enough in time to be seen in the 40Mhz domain. My question is, s...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- In fact you indeed _need_ constraints, but the good news is that you get the constraints you need by simply using the Altera extension to SDC "derive_pll_clocks". Make sure you do not place the two clocks in different clock groups nor cut the timing paths. Timequest will report the clock to clock transfers. --- Quote End --- OK I use derive_pll_clocks as you suggest. The design is very simple so I don't use clock groups. Thanks
