RTL coding

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Hi everybody,

I don't know if my thread is legal in this forum, but i expect everyone help me.

i have project about optimize timing the design on verilog code, but i can not find any documents of this topic. Remember that only on RTL code such as you use paralell coding style... , not by comment line such as "optimize_ timing...."....

Anyone help me?

Thanks all,

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Hi,

it is not clear to me what you would like to achieve ? Do you have a design which does not

achieve the required clock speed ?

Kind regards

GPK

Assume, my design operate with 200MHz (it will report on Quartus ii tool), but i want this design can operate at higher clock, 230 MHz... So, i must optimize my code verilog for this purpose. I know many tools support command line to optimize( give design the constrain), but i want change my verilog code to optimize,such as use late arriving signal,mux parallel for mux serial... :)

Example : you use select adder for normal adder because select adder operate parallel so it can be faster.

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Assume, my design operate with 200MHz (it will report on Quartus ii tool), but i want this design can operate at higher clock, 230 MHz... So, i must optimize my code verilog for this purpose. I know many tools support command line to optimize( give design the constrain), but i want change my verilog code to optimize,such as use late arriving signal,mux parallel for mux serial... :)

Example : you use select adder for normal adder because select adder operate parallel so it can be faster.

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Hi,

lets do the tools most of the work. I would start with setting the clock to the higher frequency. Run Quartus and analyze the timing. Locate the design part which does not achieve the required clock speed. If it turns out e.g. that your additions are to slow add some register stage between the adder, re-run Quartus and chek the timing again.

Kind regards

GPK

can u explain why u use register? using register have delay in it, so timing path will longer. If u mean using more clock in the design, i think it is not good becase the design have stable number clock for operation.

P/S : my project relate to GCD algorithm.

Assuming all design registers are clocked by the same clock, than the maximum clock speed will defined by the longest timing path between two registers. Splitting the related operation in multiple cycles ("pipelining") and adjusting the cycle delay of parallel pathes respectively increases the maximum clock speed. Although the design's latency increases, the throughput can be usually improved.

Regarding optimization, you can assume that Quartus basically utilizes most available means to achieve the specified timing. The timing analysis tells, if it succeeded. There is however a number of synthesis settings, that can be modified either through a Quartus menu or HDL synthesis attributes. Apart from a lot of detail parameters, there's mainly one parameter, that can actually improve synthesis results at cost of higher compilation time, it's "Timing-Driven Synthesis".