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Hi everybody,
I don't know if my thread is legal in this forum, but i expect everyone help me.
i have project about optimize timing the design on verilog code, but i can not find any documents of this topic. Remember that only on RTL code such as you use paralell coding style... , not by comment line such as "
optimize_ timing...."....
Anyone help me?
Thanks all,
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Hi,
it is not clear to me what you would like to achieve ? Do you have a design which does not
achieve the required clock speed ?
Kind regards
GPK
Honored Contributor
