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Altera_Forum's avatar
Altera_Forum
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15 years ago

RTL coding

Hi everybody, I don't know if my thread is legal in this forum, but i expect everyone help me. i have project about optimize timing the design on verilog code, but i can not find any documents o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Assume, my design operate with 200MHz (it will report on Quartus ii tool), but i want this design can operate at higher clock, 230 MHz... So, i must optimize my code verilog for this purpose. I know many tools support command line to optimize( give design the constrain), but i want change my verilog code to optimize,such as use late arriving signal,mux parallel for mux serial... :)

Example : you use select adder for normal adder because select adder operate parallel so it can be faster.