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Altera_Forum's avatar
Altera_Forum
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15 years ago

RTL coding

Hi everybody, I don't know if my thread is legal in this forum, but i expect everyone help me. i have project about optimize timing the design on verilog code, but i can not find any documents o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

can u explain why u use register? using register have delay in it, so timing path will longer. If u mean using more clock in the design, i think it is not good becase the design have stable number clock for operation.

P/S : my project relate to GCD algorithm.