RTL coding

Assuming all design registers are clocked by the same clock, than the maximum clock speed will defined by the longest timing path between two registers. Splitting the related operation in multiple cycles ("pipelining") and adjusting the cycle delay of parallel pathes respectively increases the maximum clock speed. Although the design's latency increases, the throughput can be usually improved.

Regarding optimization, you can assume that Quartus basically utilizes most available means to achieve the specified timing. The timing analysis tells, if it succeeded. There is however a number of synthesis settings, that can be modified either through a Quartus menu or HDL synthesis attributes. Apart from a lot of detail parameters, there's mainly one parameter, that can actually improve synthesis results at cost of higher compilation time, it's "Timing-Driven Synthesis".