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Assume, my design operate with 200MHz (it will report on Quartus ii tool), but i want this design can operate at higher clock, 230 MHz... So, i must optimize my code verilog for this purpose. I know many tools support command line to optimize( give design the constrain), but i want change my verilog code to optimize,such as use late arriving signal,mux parallel for mux serial... :)
Example : you use select adder for normal adder because select adder operate parallel so it can be faster.
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Hi,
lets do the tools most of the work. I would start with setting the clock to the higher frequency. Run Quartus and analyze the timing. Locate the design part which does not achieve the required clock speed. If it turns out e.g. that your additions are to slow add some register stage between the adder, re-run Quartus and chek the timing again.
Kind regards
GPK
Honored Contributor
