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Altera_Forum's avatar
Altera_Forum
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12 years ago

Ring oscillator design issue

Hello

i designed a ring oscillator (VHDL) with an up-counter to display its output. The ring oscillators' (80 inverters) output feeds into the clock input to the up-counter and the counter should displays output for each clock pulse.

The challenge am having is that the ring oscillators' frequency seems too fast that the counter counts very fast (count/step not visible to human eyes) and displays maximum counts within micro seconds, when implemented on my DE 3 (STRATIX III). How can i make oscillators frequency slow so that my design will be suitable for usage?

i understand increasing the number of inverters in the ring oscillator will reduce its frequency, but that could affect the application. I dont know if am missing something in the Timing Characteristics of the device and if that is what's affecting? i never want into Timing xtics since i started using FPGA.

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I presume that you coded the inverter chain in a way that keeps it during design optimization. The post synthesis netlist viewer can tell.

    Secondly you'll probably want to implement a clock divider.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Checked the Netlist viewer, not too sure if the compiler optimized the design. Attached is the code for the ring oscillator and the netlist viewer snapshot.

    --- Quote Start ---

    I presume that you coded the inverter chain in a way that keeps it during design optimization. The post synthesis netlist viewer can tell.

    clock divider, howz dat done???

    Secondly you'll probably want to implement a clock divider.

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    I presume that you coded the inverter chain in a way that keeps it during design optimization. The post synthesis netlist viewer can tell.

    Secondly you'll probably want to implement a clock divider.

    --- Quote End ---

    Is there a way of forcing the compiler not to optimize the design for logic utilization??? And if there is hw?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    You made it basically right (using syn_keep). Why don't you look into the delay_line block?

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    This is what I saw in an Altera supplied .vhd file: 

    
	component lcell
		port (
			a_in : in std_logic;
			a_out : out std_logic);
		end component;
		
	signal	ringoscillator	:	std_logic ;
	signal	lc1_AOut		:	std_logic ;
	signal	lc2_AOut		:	std_logic ;
	...
	-- generate an internal ring oscillator clock running fast
	--ringoscillator	<=	not lcell( not lcell( not lcell( not lcell( not lcell( ringoscillator  ) )  ) ) ) ;
	-- VHDL needs components
	lc1 : lcell port map( not ringoscillator or Reset , lc1_AOut) ; -- the Rest will kick it?
	lc2 : lcell port map( not lc1_AOut , lc2_AOut) ;
	lc3 : lcell port map( not lc2_AOut , ringoscillator) ;
--	lc3 : lcell port map( not lc2_AOut , lc3_AOut) ;
--	lc4 : lcell port map( not lc3_AOut , lc4_AOut) ;
--	lc5 : lcell port map( not lc4_AOut , ringoscillator) ;

    I added the Reset signal, not sure that's necessary though. And I understand this is not as pure as the syn_keep attribute, but it works.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Why don't you look into the delay_line block?

    --- Quote End ---

    I guess am right for the delay block??? I just gonna add some FF. thanks
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    This is what I saw in an Altera supplied .vhd file: 

    
	component lcell
		port (
			a_in : in std_logic;
			a_out : out std_logic);
		end component;
		
	signal	ringoscillator	:	std_logic ;
	signal	lc1_AOut		:	std_logic ;
	signal	lc2_AOut		:	std_logic ;
	...
	-- generate an internal ring oscillator clock running fast
	--ringoscillator	<=	not lcell( not lcell( not lcell( not lcell( not lcell( ringoscillator  ) )  ) ) ) ;
	-- VHDL needs components
	lc1 : lcell port map( not ringoscillator or Reset , lc1_AOut) ; -- the Rest will kick it?
	lc2 : lcell port map( not lc1_AOut , lc2_AOut) ;
	lc3 : lcell port map( not lc2_AOut , ringoscillator) ;
--	lc3 : lcell port map( not lc2_AOut , lc3_AOut) ;
--	lc4 : lcell port map( not lc3_AOut , lc4_AOut) ;
--	lc5 : lcell port map( not lc4_AOut , ringoscillator) ;

    I added the Reset signal, not sure that's necessary though. And I understand this is not as pure as the syn_keep attribute, but it works.

    --- Quote End ---

    Thanks... well noted