Ring oscillator design issue

This is what I saw in an Altera supplied .vhd file:

	component lcell
		port (
			a_in : in std_logic;
			a_out : out std_logic);
		end component;
		
	signal	ringoscillator	:	std_logic ;
	signal	lc1_AOut		:	std_logic ;
	signal	lc2_AOut		:	std_logic ;
	...
	-- generate an internal ring oscillator clock running fast
	--ringoscillator	<=	not lcell( not lcell( not lcell( not lcell( not lcell( ringoscillator  ) )  ) ) ) ;
	-- VHDL needs components
	lc1 : lcell port map( not ringoscillator or Reset , lc1_AOut) ; -- the Rest will kick it?
	lc2 : lcell port map( not lc1_AOut , lc2_AOut) ;
	lc3 : lcell port map( not lc2_AOut , ringoscillator) ;
--	lc3 : lcell port map( not lc2_AOut , lc3_AOut) ;
--	lc4 : lcell port map( not lc3_AOut , lc4_AOut) ;
--	lc5 : lcell port map( not lc4_AOut , ringoscillator) ;