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Altera_Forum's avatar
Altera_Forum
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12 years ago

Ring oscillator design issue

Hello i designed a ring oscillator (VHDL) with an up-counter to display its output. The ring oscillators' (80 inverters) output feeds into the clock input to the up-counter and the counter ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Checked the Netlist viewer, not too sure if the compiler optimized the design. Attached is the code for the ring oscillator and the netlist viewer snapshot.

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I presume that you coded the inverter chain in a way that keeps it during design optimization. The post synthesis netlist viewer can tell.

clock divider, howz dat done???

Secondly you'll probably want to implement a clock divider.

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