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Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Reset controller Ip's rx_digitalreset never going to LOW

HI,

I am using Reset controller, ATX pll and native phy in my project to use dynamic reconfiguration.

I have connected all signals as mentioned in user guide, and created a simulation model.

as per my understanding by applying reset to Reset_controller IP, it will generate reset sequence for native phy, but

tx_digitalreset is going low and i am getting tx_ready signal high.

but my Reset controllers rx_digitalreset is always high,

i am unable to figure out this issue,

This behavior is same for 1000us

please see the snapshot and suggest solution.

Regards,

Rajesh

5 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi Rajesh,


    As I understand it, you have some inquiries related to the rx_digitalreset behavior. For your information, the rx_digitalreset is dependent on the rx_is_lockedtodata. Only after the CDR achieved lock-to-data mode, the rx_digitalreset will be de-asserted. In your screenshot, it seems like the rx_is_lockedtodata = low.


    Please let me know if there is any concern. Thank you.


    • Rk_Athram's avatar
      Rk_Athram
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago
      Hi @CheePin_C_Intel,

      Thank you for your quick response.
      I have checked my native phy is not generating rx_clkout is always low.
      Tx_clkout is ok.
      If I understand unless CDR locks I will not get rx_clkout signal

      So what is the condition to CDR get locked?
      What points I am missing !what I should consider!
  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    For your information, the first thing after coming out from reset, the CDR will need to achieve lock-to-ref (LTR) mode. In this mode, the CDR will lock to the CDR refclk. When it has achieved LTR (rx_is_lockedtoref go high), you should start to observe rx_clkout signal output.


    Just to check with you if you are observing rx_is_lockedtoref go high or toggling?


    The general condition for CDR to get locked to refclk are correct refclk frequency, signal integrity of refclk meeting the datasheet specs, correct reset sequence, successful calibration, stable & free-running refclk during power up and stable & free-running calibration clock during power up. You can further investigate into these.


    By the way, what is the specific device that you are using?


    Please let me know if there is any concern. Thank you.


  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.