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Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Reset controller Ip's rx_digitalreset never going to LOW

HI, I am using Reset controller, ATX pll and native phy in my project to use dynamic reconfiguration. I have connected all signals as mentioned in user guide, and created a simulation model. ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


For your information, the first thing after coming out from reset, the CDR will need to achieve lock-to-ref (LTR) mode. In this mode, the CDR will lock to the CDR refclk. When it has achieved LTR (rx_is_lockedtoref go high), you should start to observe rx_clkout signal output.


Just to check with you if you are observing rx_is_lockedtoref go high or toggling?


The general condition for CDR to get locked to refclk are correct refclk frequency, signal integrity of refclk meeting the datasheet specs, correct reset sequence, successful calibration, stable & free-running refclk during power up and stable & free-running calibration clock during power up. You can further investigate into these.


By the way, what is the specific device that you are using?


Please let me know if there is any concern. Thank you.