reconfig PLL IP do not respond to user logic

Hi Intel Community,

I'm working on a project involving dynamic PLL reconfiguration using Altera/Intel PLL and PLL Reconfig IP cores in a Cyclone V FPGA. I've followed the steps outlined in the PLL Reconfig documentation, but my PLL reconfig does not seem to respond to my controller logic.

Setup Details:

FPGA Device: Cyclone V
Intel Quartus Prime Version: 18.1
PLL IP Core: Intel FPGA PLL
PLL Reconfig IP Core: Intel FPGA PLL Reconfig

Steps Implemented:

• Generated PLL and PLL Reconfig IP cores.
• Connected the reconfig_to_pll and reconfig_from_pll buses between the PLL Reconfig and PLL instances.
• Implemented the state machine for dynamic reconfiguration.
• Use Modelsim to verify the result but PLL and PLL Reconfig have no value.

and my control logic behavior match from the PLL Reconfig doc

I also attached my testbench and vhdl files below

Any help or pointers would be greatly appreciated!

Thank you in advance!