Forum Discussion
Allan6
New Contributor
New Contributorreconfig PLL IP do not respond to user logic
Hi Intel Community, I'm working on a project involving dynamic PLL reconfiguration using Altera/Intel PLL and PLL Reconfig IP cores in a Cyclone V FPGA. I've followed the steps outlined in the PLL R...
AqidAyman_Altera
Regular Contributor
Regular ContributorHi,
I really apologies as I am having difficulty reproducing the issue that you are facing.
However, I found this article that might be able to help you:
Allan6New Contributor
New ContributorHi,
Thank you for the replay
So I does that mean you have a working project if that is the case can you send me the project you have
Thank you for the assistance
