Forum Discussion
Allan6
New Contributor
New Contributorreconfig PLL IP do not respond to user logic
Hi Intel Community, I'm working on a project involving dynamic PLL reconfiguration using Altera/Intel PLL and PLL Reconfig IP cores in a Cyclone V FPGA. I've followed the steps outlined in the PLL R...
AqidAyman_Altera
Regular Contributor
Regular ContributorYou can refer to this tutorial video that demonstrate PLL reconfiguration utilizing the PLL IP and Reconfig PLL IP in Quartus.
