Forum Discussion
Allan6
New Contributor
New Contributorreconfig PLL IP do not respond to user logic
Hi Intel Community, I'm working on a project involving dynamic PLL reconfiguration using Altera/Intel PLL and PLL Reconfig IP cores in a Cyclone V FPGA. I've followed the steps outlined in the PLL R...
AqidAyman_Altera
Regular Contributor
Regular ContributorHello,
Apologize for the delay response.
Let me try to follow your steps and see if can reproduce the same issue from my side and report to you back.
Appreciate your patience.
Allan6New Contributor
New ContributorHello,
No problem at all. I appreciate your follow-up. Have you had a chance to try the steps I mentioned earlier? Were you able to reproduce the issue on your side?
Please let me know if you have any progress or need further information from me.
