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YogeshaDG's avatar
YogeshaDG
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21 days ago

Cyclone IV E(EP4CE30) FPGA JTAG and USB-Blaster

Hi Team, I am working with a Cyclone IV E FPGA(EP4CE30), where all my banks (Bank 1–8) have VCCIO = 3.3V. The FPGA core voltage is 1.2V, and the PLL supply is 2.5V. I am configuring the FPGA in Pass...
Configuration
Core Logic
Power
Programmable Logic Device
AqidAyman_Altera's avatar
AqidAyman_Altera
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13 days ago

Dear Customer,

Let me know if you have any additional questions. 

I will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

Thank you for engaging with us!

Best regards,
Altera Technical Support

  • YogeshaDG's avatar
    YogeshaDG
    Icon for New Contributor rankNew Contributor
    5 days ago

    Hi, thanks for the quick support.

    I assume we will follow the same approach for the configuration pins as well. I am planning to configure the Cyclone IV E FPGA in Passive Serial (PS) mode using:

    • Single-Device PS Configuration Using an External Host (as shown in Figure 8–13)
    • PS Configuration Using a Download Cable (as shown in Figure 8–17)

    I believe the pull-up resistor should be connected to VCCA (2.5 V). If you have any concerns or suggestions regarding this, please share your thoughts.

    i have attached my draft schematic for your reference.

     

    • AqidAyman_Altera's avatar
      AqidAyman_Altera
      Icon for Regular Contributor rankRegular Contributor
      1 day ago

      Dear Customer,

      I'm glad that your issue is resolved. I will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

      Thank you for engaging with us!

      Best regards,
      Altera Technical Support