Contributor
Regular ContributorHi Brian,
The Cyclone® V Pin Connection Guidelines state: “Connect these pins (VCCIO) to a power supply” Your test results align with the expectations, where when you left VCCIO floating, it can cause programming failure. For best and safest device hardware configuration, always connect VCCIO to the correct supply for every I/O bank, including BANK 5A/5B.
Reference: Cyclone® V GX, GT, E, SX, ST and SE Device Family Pin Connection Guidelines
Regards,
Aqid
ContributorThen this is violating the HMC standard. When slot cards are not used the VCCIO could be floated and no supplied.
I cannot see the correlation between VCCIO and JTAG program fail.
VCCIO had nothing to do with JTAG scan unless JTAG is located in VCCIO 5A/5B.
VCCPGM or VCCIO BANK 3 is only the possible IO bank that can affected.
So which handbook or document have detail info on such.
Thanks,
Brian
Regular ContributorHi Brian,
May I know what the error message you observed on the JTAG programs?
Regards,
Aqid
ContributorI lost the data on that forgot to screen capture the board is testing on other side.
I do recall the Quartus report wrong ID and always stuck on 93% final stage.
The auto detect can sense both HPS and FPGA.
All the tools are used to work properly on other C5 board and since the use of it.
So the only factor is the board and the IO bank.
When BANK 5A/B is forced to supply VCCIO there are no issue on JTAG programming.
So please if there are any info that are not welly documented please share.
As BANK 5A/B do not have any relationship to JTAG or PGM bank as least from documents I studied.
Thanks,
Brian
