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Altera_Forum's avatar
Altera_Forum
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11 years ago

re: clk gating in fpga design

hi,

i have an rtl design which has a reference clock (100M) going into a verilog-coded divider module (to generate 50M and 25M clks) and then a verilog-coded clk-mux module (to select either 25M or 50M clk, going into the rest of the system). i also have corresponding clk-gate modules for the clock going into the system

refclk -> clk-divider -> clk-mux -> clk-gate -> clk going into rest of the system/processes

as mentioned, the divider, mux, clk-gate is coded in verilog (they are not IPs of any sort).

i wanted to know that -

1) when i synthesize such a design in quartusII (for arria10 FPGA), then do the clk-divider, clk-mux, clk-gate modules result in gated clocks?

2) if yes, where in the timing report/synth report for quartusII, can i see a report for such gated clocks?

3) also - are such gated clocks bad for the design?

i have read that clk gating (in any way) removes the clk from the dedicated clk route and puts it into the logic fabric thereby adding skew into the design. does that hold true for arria10 FPGAs too? and is this skew always considered bad? and if yes, within what range, is the skew because of clk-gating acceptable?

help :)

z.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi,

    From experience, I have encountered me issues when trying to do clock gating in FPGA design. I would recommend using PLL to derive other clock frequency and clock control block to enable/disable the clock.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    1) Yes. You are creating a design, part of which is being driven by a gated clock. Perhaps the only bit that isn't is your clock divider logic.

    2) All clocks will be reported. However, you're likely to see large, unwanted skews on your derived clocks.

    3) Yes. Generally gated clocks are bad for a design. They can be useful for very small sections of logic. However, I wouldn't consider clocking any 'significant' amount of logic with one. Using a gated clock will mean the clock is routed and won't use the dedicated clock routing.

    Read the 'register-to-register' Timing section (page 12-4) of the timing closure and optimization (https://www.altera.co.jp/ja_jp/pdfs/literature/hb/qts/qts_qii52005.pdf) chapter of the quartus ii handbook. This covers this well and refers to various bad practices - including gated clocks.

    I'd also suggest putting a very small design together that creates and uses a gated clock. Constrain it, run it through Quartus and look at the timing reports in TimeQuest.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Your design creates gated clocks, which are bad. This is the case for all current FPGAs. You can force gated clocks onto clock nets, but it's not recommended and should be avoided.

    If you are generating a /2 and /4 clocks, then generating clock enables instead is relatively straight forward. Just create a 2 bit counter. 

    
signal en_cnt : unsigned(1 downto 0) := "00";
process(clk)
begin
  if rising_edge(clk) then
    en_cnt <= en_cnt -1;
    if en_cnt = 0 then
      div_4_en <= '1';
    else
      div_4_en <= '0';
    end if;
  end if;
end process;
div_2_en <= en_cnt(0);

    doing this also allows you to specify multi_cycle_paths on all registers using the /2 and /4 enables, making timing much easier.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    hi all,

    thanks for the inputs. after reading the replies, is my understanding correct that the actual clk_gate module will only be the one that leads to gated clocks in the design?

    and having a verilog coded clk divider or verilog coded clk mux module (which can be configured via registers) will not lead to gated clocks or will not harm the design in any way (like large skews)?

    is my understanding correct?

    or any type of logic on the clk route (be it a verilog coded divider or mux) will lead to a gated clock thus increasing the skew and hampering the design?

    i am putting together small design with dividers, mux etc. to check but in case someone can confirm the above, that would be great too ...

    thanks!

    z.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Any type of clock gating takes the clock off the high speed nets, so the clock arrives at all the registers at different times, causing all sorts of issues.

    Moral of the story - dont create gated clocks AT ALL.