Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

re: clk gating in fpga design

hi, i have an rtl design which has a reference clock (100M) going into a verilog-coded divider module (to generate 50M and 25M clks) and then a verilog-coded clk-mux module (to select either 25M o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Any type of clock gating takes the clock off the high speed nets, so the clock arrives at all the registers at different times, causing all sorts of issues.

Moral of the story - dont create gated clocks AT ALL.