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Altera_Forum
Honored Contributor
Honored Contributorre: clk gating in fpga design
hi, i have an rtl design which has a reference clock (100M) going into a verilog-coded divider module (to generate 50M and 25M clks) and then a verilog-coded clk-mux module (to select either 25M o...
Altera_ForumHonored Contributor
Honored ContributorAny type of clock gating takes the clock off the high speed nets, so the clock arrives at all the registers at different times, causing all sorts of issues.
Moral of the story - dont create gated clocks AT ALL.
