re: clk gating in fpga design

hi all,

thanks for the inputs. after reading the replies, is my understanding correct that the actual clk_gate module will only be the one that leads to gated clocks in the design?

and having a verilog coded clk divider or verilog coded clk mux module (which can be configured via registers) will not lead to gated clocks or will not harm the design in any way (like large skews)?

is my understanding correct?

or any type of logic on the clk route (be it a verilog coded divider or mux) will lead to a gated clock thus increasing the skew and hampering the design?

i am putting together small design with dividers, mux etc. to check but in case someone can confirm the above, that would be great too ...

thanks!

z.