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Altera_Forum
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10 years ago

re: clk gating in fpga design

hi, i have an rtl design which has a reference clock (100M) going into a verilog-coded divider module (to generate 50M and 25M clks) and then a verilog-coded clk-mux module (to select either 25M o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi,

From experience, I have encountered me issues when trying to do clock gating in FPGA design. I would recommend using PLL to derive other clock frequency and clock control block to enable/disable the clock.