re: clk gating in fpga design

1) Yes. You are creating a design, part of which is being driven by a gated clock. Perhaps the only bit that isn't is your clock divider logic.

2) All clocks will be reported. However, you're likely to see large, unwanted skews on your derived clocks.

3) Yes. Generally gated clocks are bad for a design. They can be useful for very small sections of logic. However, I wouldn't consider clocking any 'significant' amount of logic with one. Using a gated clock will mean the clock is routed and won't use the dedicated clock routing.

Read the 'register-to-register' Timing section (page 12-4) of the timing closure and optimization (https://www.altera.co.jp/ja_jp/pdfs/literature/hb/qts/qts_qii52005.pdf) chapter of the quartus ii handbook. This covers this well and refers to various bad practices - including gated clocks.

I'd also suggest putting a very small design together that creates and uses a gated clock. Constrain it, run it through Quartus and look at the timing reports in TimeQuest.

Cheers,

Alex