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Altera_Forum's avatar
Altera_Forum
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10 years ago

re: clk gating in fpga design

hi, i have an rtl design which has a reference clock (100M) going into a verilog-coded divider module (to generate 50M and 25M clks) and then a verilog-coded clk-mux module (to select either 25M o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Your design creates gated clocks, which are bad. This is the case for all current FPGAs. You can force gated clocks onto clock nets, but it's not recommended and should be avoided.

If you are generating a /2 and /4 clocks, then generating clock enables instead is relatively straight forward. Just create a 2 bit counter. 


signal en_cnt : unsigned(1 downto 0) := "00";
process(clk)
begin
  if rising_edge(clk) then
    en_cnt <= en_cnt -1;
    if en_cnt = 0 then
      div_4_en <= '1';
    else
      div_4_en <= '0';
    end if;
  end if;
end process;
div_2_en <= en_cnt(0);

doing this also allows you to specify multi_cycle_paths on all registers using the /2 and /4 enables, making timing much easier.