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Regular ContributorHi Jayden ,
Lane 9 appears to decode the TS2 sequence correctly. Lane 8 shows COM (K28.5) and PAD (K23.7) correctly, but the symbols after that are unstable / corrupted.
>> I see you are using x16, do you occupied all of the 16 lane ?
>> Is it only lane 9 and lane 8 got problem and other lane act as what you expected ?
>> Do you tested in gen2 ? or this issue only seeing in gen1 ?
What mode of the pipe direct you trying to perform ?
Reset sequence or speed change ?
IF I understand correctly from your case description , I assume you are using reset sequence.
IF Yes, please check the signal sequence example under
https://docs.altera.com/r/docs/683501/25.1.1/r-tile-avalon-streaming-ip-for-pci-express-user-guide/pipe-direct-reset-sequence
Please do ensure that those sequence are strictly been followed.
Based on my experience and understanding , once the system entering polling.configuration substate, the a transmitter will stop sending TS1s and start sending TS2s, still with PAD set for the Link and Lane numbers. The purpose of the change to sending TS2s instead of TS1s is to advertise to the link partner that this device is ready to proceed to the next state in the state machine. It is a handshake mechaȬ nism to ensure that both devices on the link proceed through the LTSSM together. Neither device can proceed to the next state until both devices are ready. The way they advertise they are ready is by sending TS2 orderedȬsets. So once a device is both sending AND receiving TS2s, it knows it can proceed to the next state because it is ready and its link partner is ready too.
BUT I not sure what happening with your system, perhaps checking back the reset sequence can be a good start for us.
Regards,
Wincent_Altera
