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Altera_Forum's avatar
Altera_Forum
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16 years ago

Questions regading PLL, phase aligned clocks and synchronization of reset

*** PLL phase aligned clocks:

------------------------------

I Am using PLL in my design, The input to PLL is 80 Mhz clock, PLL generates

phase aligned slow clock of 40Mhz. Farther in the design I use this 40 Mhz

clock along with 80 Mhz as if there is only one clock domain, no synchronization.

I assum that since the clocks are phase aligned, no synchronization needed

Here is My First question: Is it OK?

I have doubts, may be it's better to generate two clocks out of 80Mhz, 40Mhz and 80 Mhz

so all clock will be same "nature", than to use one PLL generated clock (40Mhz) and one external (80 Mhz),

what do you think?

*** Synchroniztion of reset to PLL generated Clock:

-----------------------------------------------------

As before, I have PLL that generates 40 Mhz phased aligned clock out of 80 Mhz clock, The design is feed by single asynchronous logic reset.

Usually, In the design that do not involves PLL, I synchronize the reset before it is used in the design I synchronize it in the following way:

- the reset activation is asynchronous

- the negation is synchronous to clock.

The aim of this synchronization is to insure that when the design exits out of

reset all modules in the design start working the same clock.

When PLL is used some complications appear...

To what clock should I syncronize the negation?

PLL receives the reset as is, before the synchronization.

As before, I wish to insure, that all the design starts working the same clock after reset negation. How do I achive this, baring in mind that In side the design I Use clock generated in PLL?

Is it safe to synchronize reset negation to the ouput of PLL clock?

I have doubts because, I don't quite sure what happens with 40 Mhz clock after power reset

1) When does PLL start generation of 40 Mhz clock ?

Is it only after negation of logic reset, or right after power reset?

If it goes it only after logic reset, then at the first moment after

negation of the reset, the clock of 40 Mhz is not well defined, abviously it is not save to synchronize the reset to it.

2) May be, the design should use reset that is "anded" with not(locked flag)

and then be synchronized to 40 Mhz clock .

[locked flag is flag that PLL rises when it finishes the clock generation]?

Thak you, feel free to share your thoughts !

Greg.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    With regards to the clock: You are correct in assuming that Quartus will be aware of the relationship between the 80Mhz and 40MHz clocks. However, I would suggest generating a 80MHz clock from the PLL and using that to clock your fabric. Then you can be sure that the 80 and 40 will track each other.

    With regards to reset: It is not in my opinion simply sufficent to synchronously negate the reset with a flip-flop. You could use this method but you would at the very least need to add flip-flop stages for metastability and you would need to restrict Quartus to prevent it from replicating that final reset flip-flop. My preferred method is a reset counter.

    Here is a rather lengthy discussion on the subject:

    http://www.alteraforum.com/forum/showthread.php?t=6602&referrerid=2226

    Now with regards to the reset across the two clock domains. What I have done in the past is generate a reset in the slower clock domain (40MHz in your case), then generate a second reset off of the 80MHz clock that will be used as your reset for all logic. 

                       _____       _____
     40MHz - _____|     |_____|     |__
             __    __    __    __    __
     80MHz -   |__|  |__|  |__|  |__|  
             __
     reset -   |_______________________
                   _____________________
reset_n_40 - _____|
                         _______________
   reset_n - ___________|
         First active clock --^

    Now my diagram isn't showing the delayed reset from the counter but it's just to illustrate the synchronization of the reset signals.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I like to add a few thoughts. Unfortunately, they don't simplify the discussion, I fear.

    - If you have an external reset to your system, you may want to reset the PLL too, because it's the only way to restore defined phase relations of PLL outputs respectively PLL to input clock, if they have been lost, e.g. due to an input clock failure.

    - Self reset of the PLL in case of unlock can basically achieve this too, but an explicite reset option should be preferred in my opinion.

    - The reset to the design part clocked from the PLL should be released after PLL lock.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thank you All,

    I'll try to sum up:

    1) If one wishes to use phase aligned clocks (to avoid signals synchronization through clock domains), he should generate all the clocks by the PLL.

    2) There should be two different resets in the design, one reset that goes directly to PLL with additional logic that can activate it when PLL unlocks.

    The other reset for the rest of the design, that reset should be synchronized (the negation) to the clocks by counter, If the counter long enough, no need to look at "locked" flag of PLL.

    Regarding the advise to generate clocks by PLL, is it because the resulting clocks are more tolerate to external noise? Or because the phase alignment is more accurate?

    I have done several experiments with PLL in my design, it seems as if when I do not generate all the clocks by PLL (rather one is external 80 MHz and the other is PLL generated 40Mhz) the design becomes metastable! It's

    weird since in either way I generate phase aligned clocks. Seems like the clock are truly phased aligned only when both come out of PLL, what may I do wrong that I get those results?

    Thank you.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The PLL is constantly tracking the input clock to keep the outputs phase aligned. The PLL's ability to track the phase of the input clock is limited by it's bandwidth. Although on average the PLL outputs are phase aligned with the input clock, at any given instant, there is an error between the two. If at any given moment this error in phase becomes large enough to eat away at your setup and hold margins in those domains where you cross between the two clocks, you will get errors.

    Therefore, if you want to decrease the phase error between the input and output clocks, you want to create the PLL with higher bandwidth settings. This results in higher jitter on the output clocks because the PLL is able to adjust the VCO more rapidly.

    When both of your clocks are generated by the PLL, they are actually generated by the same clock (VCO). Because of this the error between their phases for all practical purposes can be assumed to be zero.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Jakobjones, thank you for your quick reply

    You basicly say that the phase alignment to externakl clock is zero on average.

    In general I thought that if external clock has well defined frequency, then the phase aligned clock will be aligned to it in every signle clock rise.

    Thank very much , it was great help for me!