Questions regading PLL, phase aligned clocks and synchronization of reset

I like to add a few thoughts. Unfortunately, they don't simplify the discussion, I fear.

- If you have an external reset to your system, you may want to reset the PLL too, because it's the only way to restore defined phase relations of PLL outputs respectively PLL to input clock, if they have been lost, e.g. due to an input clock failure.

- Self reset of the PLL in case of unlock can basically achieve this too, but an explicite reset option should be preferred in my opinion.

- The reset to the design part clocked from the PLL should be released after PLL lock.