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Altera_Forum
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16 years ago

Questions regading PLL, phase aligned clocks and synchronization of reset

*** PLL phase aligned clocks: ------------------------------ I Am using PLL in my design, The input to PLL is 80 Mhz clock, PLL generates phase aligned slow clock of 40Mhz. Farther i...
Altera_Forum's avatar
Altera_Forum
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16 years ago

The PLL is constantly tracking the input clock to keep the outputs phase aligned. The PLL's ability to track the phase of the input clock is limited by it's bandwidth. Although on average the PLL outputs are phase aligned with the input clock, at any given instant, there is an error between the two. If at any given moment this error in phase becomes large enough to eat away at your setup and hold margins in those domains where you cross between the two clocks, you will get errors.

Therefore, if you want to decrease the phase error between the input and output clocks, you want to create the PLL with higher bandwidth settings. This results in higher jitter on the output clocks because the PLL is able to adjust the VCO more rapidly.

When both of your clocks are generated by the PLL, they are actually generated by the same clock (VCO). Because of this the error between their phases for all practical purposes can be assumed to be zero.

Jake