Questions regading PLL, phase aligned clocks and synchronization of reset

Thank you All,

I'll try to sum up:

1) If one wishes to use phase aligned clocks (to avoid signals synchronization through clock domains), he should generate all the clocks by the PLL.

2) There should be two different resets in the design, one reset that goes directly to PLL with additional logic that can activate it when PLL unlocks.

The other reset for the rest of the design, that reset should be synchronized (the negation) to the clocks by counter, If the counter long enough, no need to look at "locked" flag of PLL.

Regarding the advise to generate clocks by PLL, is it because the resulting clocks are more tolerate to external noise? Or because the phase alignment is more accurate?

I have done several experiments with PLL in my design, it seems as if when I do not generate all the clocks by PLL (rather one is external 80 MHz and the other is PLL generated 40Mhz) the design becomes metastable! It's

weird since in either way I generate phase aligned clocks. Seems like the clock are truly phased aligned only when both come out of PLL, what may I do wrong that I get those results?

Thank you.