Questions regading PLL, phase aligned clocks and synchronization of reset

With regards to the clock: You are correct in assuming that Quartus will be aware of the relationship between the 80Mhz and 40MHz clocks. However, I would suggest generating a 80MHz clock from the PLL and using that to clock your fabric. Then you can be sure that the 80 and 40 will track each other.

With regards to reset: It is not in my opinion simply sufficent to synchronously negate the reset with a flip-flop. You could use this method but you would at the very least need to add flip-flop stages for metastability and you would need to restrict Quartus to prevent it from replicating that final reset flip-flop. My preferred method is a reset counter.

Here is a rather lengthy discussion on the subject:

http://www.alteraforum.com/forum/showthread.php?t=6602&referrerid=2226

Now with regards to the reset across the two clock domains. What I have done in the past is generate a reset in the slower clock domain (40MHz in your case), then generate a second reset off of the 80MHz clock that will be used as your reset for all logic.

                   _____       _____
     40MHz - _____|     |_____|     |__
             __    __    __    __    __
     80MHz -   |__|  |__|  |__|  |__|  
             __
     reset -   |_______________________
                   _____________________
reset_n_40 - _____|
                         _______________
   reset_n - ___________|
         First active clock --^

Now my diagram isn't showing the delayed reset from the counter but it's just to illustrate the synchronization of the reset signals.

Jake