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Honored Contributor
Honored ContributorQuestions regading PLL, phase aligned clocks and synchronization of reset
*** PLL phase aligned clocks: ------------------------------ I Am using PLL in my design, The input to PLL is 80 Mhz clock, PLL generates phase aligned slow clock of 40Mhz. Farther i...
Altera_ForumHonored Contributor
Honored ContributorJakobjones, thank you for your quick reply
You basicly say that the phase alignment to externakl clock is zero on average. In general I thought that if external clock has well defined frequency, then the phase aligned clock will be aligned to it in every signle clock rise. Thank very much , it was great help for me!
