Hello, is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?

--- Quote Start --- is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"? --- Quote End --- No. The monitors are there to generate assertion messages regarding Avalon-MM bus protocol violations. Cheers, Dave

Thanks Dave. I came across some papers which discussed about developing monitors in SVA [System Verilog Assertion Language] and it stated that these monitors can be synthesized. "This paper presents one implementation of the Open Control Protocol (OCP) monitoring on the synthesized FPGA design using the implemented library of Synthesizable SystemVerilog Assertions (SSVA). The SSVA library is developed using the layer structure of SystemVerilog assertions. It is used in implementation of the monitors for two profiles of the OCP. SSVA library and OCP monitors are then functionally verified in simulator using the test case of the processor-memory communication. The test case is then synthesized on CHIPit Platinum Edition FPGA. The implemented library and monitors can be used in many commercial and educational projects due to their simplicity and low FPGA area usage."

--- Quote Start --- I came across some papers which discussed about developing monitors in SVA [System Verilog Assertion Language] and it stated that these monitors can be synthesized. --- Quote End --- Have a look at the source code. I think you'll find it wrapped in synthesis off/on blocks so that Quartus never even sees the code. That's certainly the case for the Avalon-MM master BFM component. The complication regarding synthesized assertions, is that an assertion needs some method of reporting failures, so a synthesizeable assertion checker would need an Avalon-MM interface with a block of control/status registers so that you could check for assertion failures, and clear error counters. But if your transaction just locked up the Avalon-MM bus, how would you read that register? You really don't want your transactions to fail in real hardware. That is what verification testing is for in the simulator :) Cheers, Dave

Monitors can be synthesized but not recommended right?. I will do some reading and get back to you about this. I have just started Qsys a few weeks ago, apart from the tutorials provided by qsys are there any other online tutorials/ good books about qsys. Thank you, Aditya

--- Quote Start --- Monitors can be synthesized but not recommended right? --- Quote End --- You're missing the point. The task of a monitor is to confirm that components adhere to the bus protocol specification. If a component will violate the bus specification, then its likely the bus will lock-up, and your system will freeze. Sure you can have a watch-dog reset the bus, and perhaps have a 'reset reason' and a backtrace. But all this can be reproduced in the simulation much easier. You setup randomized bus transactions, and code coverage, etc., and make sure things are well tested. Then you can synthesize. --- Quote Start --- I will do some reading and get back to you about this. --- Quote End --- Sure. I'm not saying they don't exist, but the question is what use are they? Feel free to come up with a good reason :) --- Quote Start --- I have just started Qsys a few weeks ago, apart from the tutorials provided by qsys are there any other online tutorials/ good books about qsys. --- Quote End --- You will learn best by building components, constructing _hw.tcl files, and synthesizing them. The nice thing about this approach is that you can get Quartus to generate an _hw.tcl file for some simple components, and then read the documentation about the settings. Things will make much more sense then. The Quartus handbook has chapters on Qsys. I think alot of the component stuff is the same as the SOPC Builder stuff, so you can look at that manual too. The Qsys tutorial has layers of hierarchy, since Altera wants to show off the new features of Qsys relative to SOPC Builder. Rather than using that to learn from, try to create a design with an Avalon-MM BFM master, and an Avalon-MM slave registers interface; don't use the PIO core, write your own. Then write a SystemVerilog testbench to generate read/write transactions to your registers. You can add an Avalon-MM monitor into your testbench, and then generate transactions that violate the bus specification, eg. perform a read or write with invalid byte enables and see the assertion failure messages. You must have a tool that supports System Verilog Assertions (SVA), like the full version of Modelsim, otherwise you will not get the SVA messages. Cheers, Dave

Question about Monitor | Altera Community

117 Replies

Altera_Forum
Honored Contributor
15 years ago
can please you explain more about conduits? I read the manual did not help much!

Thanks,
Adi
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
This is what I did: I created a variation of PCI [actually no/very little variation] using Megafunction Wizard. I got a verilog file for that IP that contained variations [since I did not do any variations, I got a .v for that IP] and then I included that file in the component editor. Then the component editor generated the _hw.tcl file. Is this technique alright?

--- Quote End ---
If the IP has an Avalon interface, then yes, this would work fine.

The other way to do it, is to use the component editor to create the Avalon interfaces in an _hw.tcl file that does not include any Verilog/VHDL source. This then sets a flag in the Tcl telling it not to instantiate the IP inside the SOPC system.

The top-level SOPC system then has Avalon ports that you can connect your IP to. This would be useful if your Megawizard generated component had conduit ports or port widths that change based on generics, since you could edit the part with the MegaWizard tool, and not have to change anything in SOPC builder.

Cheers,
Dave
Altera_Forum
Honored Contributor
15 years ago
I think I just did that. This is what I did: I created a variation of PCI [actually no/very little variation] using Megafunction Wizard. I got a verilog file for that IP that contained variations [since I did not do any variations, I got a .v for that IP] and then I included that file in the component editor. Then the component editor generated the _hw.tcl file. Is this technique alright?

I dont know why Qsys is allowing this custom component[nothing but PCI] but not the actual PCI IP from Quartus 9.1 sp1.
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
Yes I get what you are saying; so, using megafunctions is same as double clicking on the ip's and changing their parameters in the system contents tab [the place where you interconnect components] right?

--- Quote End ---
Right. I think Altera has made several components that can be accessed either via the MegaWizard or via Qsys. I suspect that for the components you are interested in, you will have to write your own Qsys wrapper.

--- Quote Start ---

I am trying to add new ports such as reset etc.. for Mega IPs such as PCI - compiler.

I guess, I have to use component editor if I need to create new IP's.

--- Quote End ---
You will suffer less if you control the code; so just create the MegaWizard IP using the MegaWizard GUI, and then create your own Qsys components and their associated _hw.tcl. Once you get it working for your PCI component, it'll be easy to get it working for anything else.

Cheers,
Dave
Altera_Forum
Honored Contributor
15 years ago
Yes I get what you are saying; so, using megafunctions is same as double clicking on the ip's and changing their parameters in the system contents tab [the place where you interconnect components] right?

I am trying to add new ports such as reset etc.. for Mega IPs such as PCI - compiler.

I guess, I have to use component editor if I need to create new IP's.

Thanks,
Adi
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
when I create a variation of the component using Megafunction. Can I make the new component to show up in the IP list?
--- Quote End ---
Megafunctions and Qsys are different tools.

Not all Megafunctions have Avalon interfaces, so they cannot be used within Qsys without first creating a custom Avalon-MM or ST interface. If you used generics in your Qsys definition of the component interface, you could then pass those down to the Megafunction component.

Is that what you were asking?

Cheers,
Dave
Altera_Forum
Honored Contributor
15 years ago
Okay,I will do that. when I create a variation of the component using Megafunction. Can I make the new component to show up in the IP list?
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---

When I try to import an older system into Qsys I get the following errors and doubts:

--- Quote End ---
I haven't used Qsys to import SOPC Builder projects, so cannot help answer your questions.

Try posting a new thread with a title like "Errors when importing SOPC system into Qsys", and see if someone else can offer advice.

Cheers,
Dave
Altera_Forum
Honored Contributor
15 years ago
Hey Dave,

When I try to import an older system into Qsys I get the following errors and doubts:

errors:

1. component xxx must have an associated reset. [i edited the pins and got rid of the error for one of the simple design.]. does qsys create a global reset pin ? [ i get this for all the components]

2. it says asks me to replace pci-compiler with a compatible component. doubts

a. Why does it not complain about not finding the PCI-compiler IP in it's IP list?

b.Automatically coundits show up in all the components [What are they?(i read the manual, but not satisfied with explanation) and why are they created]. I Igonered the conduits in one of my designs: the simulation worked fine and I could also run the "compile Design without any errors"

c. Instead of creating the new system with PCIe, can I use the MegaIP wizard to modify the PCI-compiler and then add it to my Qsys system. [Any component is related with only two files right?; its verilog file and _hw.tcl file]

Thanks and have a joyous day,
Aditya
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
Got it!

--- Quote End ---
Great!

Cheers,
Dave

Forum Discussion

Question about Monitor

117 Replies

Recent Discussions

Quartus 25.1std | Signal Tap Crash

Build errors on helloworld tutorial

The Quartus Prime Lite Edition Installer 23.1

Agilex 5 RCOMP_GTS connection change and its effect on HVIO input pins

Agilex 5 GTS Reference Clock Buffer Protection