Question about Monitor

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This is what I did: I created a variation of PCI [actually no/very little variation] using Megafunction Wizard. I got a verilog file for that IP that contained variations [since I did not do any variations, I got a .v for that IP] and then I included that file in the component editor. Then the component editor generated the _hw.tcl file. Is this technique alright?

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If the IP has an Avalon interface, then yes, this would work fine.

The other way to do it, is to use the component editor to create the Avalon interfaces in an _hw.tcl file that does not include any Verilog/VHDL source. This then sets a flag in the Tcl telling it not to instantiate the IP inside the SOPC system.

The top-level SOPC system then has Avalon ports that you can connect your IP to. This would be useful if your Megawizard generated component had conduit ports or port widths that change based on generics, since you could edit the part with the MegaWizard tool, and not have to change anything in SOPC builder.

Cheers,

Dave