Question about Monitor

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when I create a variation of the component using Megafunction. Can I make the new component to show up in the IP list?

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Megafunctions and Qsys are different tools.

Not all Megafunctions have Avalon interfaces, so they cannot be used within Qsys without first creating a custom Avalon-MM or ST interface. If you used generics in your Qsys definition of the component interface, you could then pass those down to the Megafunction component.

Is that what you were asking?

Cheers,

Dave

Yes I get what you are saying; so, using megafunctions is same as double clicking on the ip's and changing their parameters in the system contents tab [the place where you interconnect components] right?

I am trying to add new ports such as reset etc.. for Mega IPs such as PCI - compiler.

I guess, I have to use component editor if I need to create new IP's.

Thanks,

Adi

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Yes I get what you are saying; so, using megafunctions is same as double clicking on the ip's and changing their parameters in the system contents tab [the place where you interconnect components] right?

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Right. I think Altera has made several components that can be accessed either via the MegaWizard or via Qsys. I suspect that for the components you are interested in, you will have to write your own Qsys wrapper.

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I am trying to add new ports such as reset etc.. for Mega IPs such as PCI - compiler.

I guess, I have to use component editor if I need to create new IP's.

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You will suffer less if you control the code; so just create the MegaWizard IP using the MegaWizard GUI, and then create your own Qsys components and their associated _hw.tcl. Once you get it working for your PCI component, it'll be easy to get it working for anything else.

Cheers,

Dave

I think I just did that. This is what I did: I created a variation of PCI [actually no/very little variation] using Megafunction Wizard. I got a verilog file for that IP that contained variations [since I did not do any variations, I got a .v for that IP] and then I included that file in the component editor. Then the component editor generated the _hw.tcl file. Is this technique alright?

I dont know why Qsys is allowing this custom component[nothing but PCI] but not the actual PCI IP from Quartus 9.1 sp1.

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This is what I did: I created a variation of PCI [actually no/very little variation] using Megafunction Wizard. I got a verilog file for that IP that contained variations [since I did not do any variations, I got a .v for that IP] and then I included that file in the component editor. Then the component editor generated the _hw.tcl file. Is this technique alright?

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If the IP has an Avalon interface, then yes, this would work fine.

The other way to do it, is to use the component editor to create the Avalon interfaces in an _hw.tcl file that does not include any Verilog/VHDL source. This then sets a flag in the Tcl telling it not to instantiate the IP inside the SOPC system.

The top-level SOPC system then has Avalon ports that you can connect your IP to. This would be useful if your Megawizard generated component had conduit ports or port widths that change based on generics, since you could edit the part with the MegaWizard tool, and not have to change anything in SOPC builder.

Cheers,

Dave

can please you explain more about conduits? I read the manual did not help much!

Thanks,

Adi

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can please you explain more about conduits?

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Conduits are the signals from your Avalon component that are not related to the Avalon bus.

For example, a PCI core for use with the Avalon bus would technically be called a PCI-to-Avalon bridge, since it maps between the two protocols. In its simplest form, the bridge would be a PCI target. A PCI target cannot become a master of the PCI bus. The PCI-to-Avalon bridge would have a PCI target interface, and an Avalon-MM master interface. The signals for the Avalon-MM master interface would connect to the SOPC system. The signals for the PCI target interface would be marked as conduit signals in the SOPC _hw.tcl file. When you generate the SOPC system, those conduit signals will be present as signals on the top-level component. You then connect those to the PCI signals on the FPGA pins.

Is that clearer?

Cheers,

Dave

Some clarifications before I get to conduits:

When I create system that can be synthesized on an FPGA the components of my system is glued by the Avalon interfaces right?

This interface is also called as System Interconnect Fabric right and is made up of Avalon Bus, right?

These conduits kick in only when the signals are going out of FPGA or if the signals are entering the FPGA right?

Now coming to what you said, If I have a PCI bus then, a conduit shows up between the PCI bus external to the FPGA and Avalon interface within the FPGA right?

When conduits show up in Qsys what should I do with them? leave them alone? since they are connected to outside of FPGA.

Also, what is the role of conduit BFMs. I am not able to imagine or get a clear mental picture of things going on with conduits!. Try simplifying it as much as possible and please explain once again. Appreciate your effort and time :-)

Thanks,

Adi

Thanks,

Adi

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Some clarifications before I get to conduits:

When I create system that can be synthesized on an FPGA the components of my system is glued by the Avalon interfaces right?

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In SOPC Builder or Qsys, when you click connections between components, you are making Avalon connections; either MM or ST.

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This interface is also called as System Interconnect Fabric right and is made up of Avalon Bus, right?

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Yeah, pretty much.

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These conduits kick in only when the signals are going out of FPGA or if the signals are entering the FPGA right?

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Entering or leaving the SOPC system. You could connect them to external signals, or you could loop them back into the SOPC system, eg., control signals from a PIO component might loop back into the system via a different conduit to enable/disable another component.

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Now coming to what you said, If I have a PCI bus then, a conduit shows up between the PCI bus external to the FPGA and Avalon interface within the FPGA right?

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Yes. All the PCI signals would be marked as conduit signals.

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When conduits show up in Qsys what should I do with them? leave them alone? since they are connected to outside of FPGA.

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I would guess you leave them unconnected. I have not used Qsys much yet. I'm not sure why the conduits show up in the GUI. Perhaps someone else can comment.

Cheers,

Dave