Hello, is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?

--- Quote Start --- is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"? --- Quote End --- No. The monitors are there to generate assertion messages regarding Avalon-MM bus protocol violations. Cheers, Dave

Thanks Dave. I came across some papers which discussed about developing monitors in SVA [System Verilog Assertion Language] and it stated that these monitors can be synthesized. "This paper presents one implementation of the Open Control Protocol (OCP) monitoring on the synthesized FPGA design using the implemented library of Synthesizable SystemVerilog Assertions (SSVA). The SSVA library is developed using the layer structure of SystemVerilog assertions. It is used in implementation of the monitors for two profiles of the OCP. SSVA library and OCP monitors are then functionally verified in simulator using the test case of the processor-memory communication. The test case is then synthesized on CHIPit Platinum Edition FPGA. The implemented library and monitors can be used in many commercial and educational projects due to their simplicity and low FPGA area usage."

--- Quote Start --- I came across some papers which discussed about developing monitors in SVA [System Verilog Assertion Language] and it stated that these monitors can be synthesized. --- Quote End --- Have a look at the source code. I think you'll find it wrapped in synthesis off/on blocks so that Quartus never even sees the code. That's certainly the case for the Avalon-MM master BFM component. The complication regarding synthesized assertions, is that an assertion needs some method of reporting failures, so a synthesizeable assertion checker would need an Avalon-MM interface with a block of control/status registers so that you could check for assertion failures, and clear error counters. But if your transaction just locked up the Avalon-MM bus, how would you read that register? You really don't want your transactions to fail in real hardware. That is what verification testing is for in the simulator :) Cheers, Dave

Monitors can be synthesized but not recommended right?. I will do some reading and get back to you about this. I have just started Qsys a few weeks ago, apart from the tutorials provided by qsys are there any other online tutorials/ good books about qsys. Thank you, Aditya

--- Quote Start --- Monitors can be synthesized but not recommended right? --- Quote End --- You're missing the point. The task of a monitor is to confirm that components adhere to the bus protocol specification. If a component will violate the bus specification, then its likely the bus will lock-up, and your system will freeze. Sure you can have a watch-dog reset the bus, and perhaps have a 'reset reason' and a backtrace. But all this can be reproduced in the simulation much easier. You setup randomized bus transactions, and code coverage, etc., and make sure things are well tested. Then you can synthesize. --- Quote Start --- I will do some reading and get back to you about this. --- Quote End --- Sure. I'm not saying they don't exist, but the question is what use are they? Feel free to come up with a good reason :) --- Quote Start --- I have just started Qsys a few weeks ago, apart from the tutorials provided by qsys are there any other online tutorials/ good books about qsys. --- Quote End --- You will learn best by building components, constructing _hw.tcl files, and synthesizing them. The nice thing about this approach is that you can get Quartus to generate an _hw.tcl file for some simple components, and then read the documentation about the settings. Things will make much more sense then. The Quartus handbook has chapters on Qsys. I think alot of the component stuff is the same as the SOPC Builder stuff, so you can look at that manual too. The Qsys tutorial has layers of hierarchy, since Altera wants to show off the new features of Qsys relative to SOPC Builder. Rather than using that to learn from, try to create a design with an Avalon-MM BFM master, and an Avalon-MM slave registers interface; don't use the PIO core, write your own. Then write a SystemVerilog testbench to generate read/write transactions to your registers. You can add an Avalon-MM monitor into your testbench, and then generate transactions that violate the bus specification, eg. perform a read or write with invalid byte enables and see the assertion failure messages. You must have a tool that supports System Verilog Assertions (SVA), like the full version of Modelsim, otherwise you will not get the SVA messages. Cheers, Dave

Question about Monitor | Altera Community

117 Replies

Altera_Forum
Honored Contributor
15 years ago
Rysc, usually I get timing errors between nodes that are related to the avalon switch fabric. How do I specify the timing constraints related to these nodes before I compile the design. [I will only know the errors after they are compiled] So in this case there is no other option other than specifying the timing exceptions in the sdc after the design right?.

I can specify the timing constraints before compilation, if it's my own design without any Avalon generated components, right?
Altera_Forum
Honored Contributor
15 years ago
You just constrain the clocks, and all downstream logic should get constrained. You might need to add false paths between clocks(can use set_clock_groups to do this). You should not be adding any false paths or multicycles directly to paths in the avalon switch fabric.
Altera_Forum
Honored Contributor
15 years ago
Okay. Thanks.
Altera_Forum
Honored Contributor
15 years ago
Hello,

I have a system built in SOPC.

Here is some background:

1. sopc: Timing Requirement met.

2. qsys: Timing Requirement not met even with 4 pipeline stages + I have followed the suggestions of Timing Optimization Advisor. [Timing error exists within NIOS component].

My Questions:

1. Apart from redesigning the system what are the other things I can do?
2. Does creating the Qsys system from scratch [rather than just upgrading the SOPC system] have any effect on the timing ? [I noticed that the Total Negative slack reduced when I built the system from scratch]

Thanks,
AA
Altera_Forum
Honored Contributor
15 years ago
Hello Rysc and Dave,

Did I ask an invalid question? :-o

Thanks,
AA
Altera_Forum
Honored Contributor
15 years ago
Hello Rysc,

In your timing analysis guide on page 32, I am not able to understand the sentence "Hold relationship means the data should get there after the latch clocks 0ns edge gets there" [2 line of the page]

Thanks,
AA
Altera_Forum
Honored Contributor
15 years ago
I am having a similar issue where I need to simulate a PCIe design where the testbench should represent the stimulus as depicted by the PC. Any recommendations of where to start? and did you use the Altera Hard IP or Soft IP blocks.

Thank you in advance.

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Question about Monitor

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