Altera_Forum
Honored Contributor
Honored ContributorQuestion about Monitor
Hello, is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?
Forum Discussion
Altera_ForumHonored Contributor
Honored ContributorYou just constrain the clocks, and all downstream logic should get constrained. You might need to add false paths between clocks(can use set_clock_groups to do this). You should not be adding any false paths or multicycles directly to paths in the avalon switch fabric.
