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Altera_Forum's avatar
Altera_Forum
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15 years ago

Question about Monitor

Hello, is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hello,

I have a system built in SOPC.

Here is some background:

1. sopc: Timing Requirement met.

2. qsys: Timing Requirement not met even with 4 pipeline stages + I have followed the suggestions of Timing Optimization Advisor. [Timing error exists within NIOS component].

My Questions:

1. Apart from redesigning the system what are the other things I can do?

2. Does creating the Qsys system from scratch [rather than just upgrading the SOPC system] have any effect on the timing ? [I noticed that the Total Negative slack reduced when I built the system from scratch]

Thanks,

AA