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Altera_Forum's avatar
Altera_Forum
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14 years ago

Question about Monitor

Hello, is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Rysc, usually I get timing errors between nodes that are related to the avalon switch fabric. How do I specify the timing constraints related to these nodes before I compile the design. [I will only know the errors after they are compiled] So in this case there is no other option other than specifying the timing exceptions in the sdc after the design right?.

I can specify the timing constraints before compilation, if it's my own design without any Avalon generated components, right?