Question about MAX10 FPGA's specification on using Altera Dual Configuration IP Core.

Thank you for your reply.

Sorry, I was wrong.

I made a mistake in writing step1.

A correct question is as follows.

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I want to reconfiguration MAX10(10M08DAU324I7G) FPGA with selecting configuration image0/1.

step1. Write register of IP Core Avalon-MM Address Map Offset:1 Bit:1=config image0or1 Bit:0=1(trigger)

step2. Wait busy signal de-asserted.

step3. ReConfiguration start.

When busy signal never de-assert, I want to abort process step2.

Please teach me maximum time (or clock cycle) of write register to busy signal de-asserted.

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It writes in the datasheet(Intel MAX10 FPGA Configuration User Guide Table34.) so.

The busy signal is generated right after the write cycle, while the configuration

image information is registered. Once busy signal is high, writing to this address

is ignored until the process is completed and the busy signal is de-asserted.

I think I have to wait busy signal de-asserted after set config_sel before set trigger reconfiguration.