Forum Discussion

YSaka7's avatar
YSaka7
Icon for New Contributor rankNew Contributor
7 years ago

Question about MAX10 FPGA's specification on using Altera Dual Configuration IP Core.

I want to reconfiguration MAX10(10M08DAU324I7G) FPGA with selecting configuration image0/1. step1. Write register of IP Core Avalon-MM Address Map Offset:0 Bit:1=config image0/1 Bit:0=1(trigger) st...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi, I don't think you are able to observed the busy signal de-asserted as the device will start reconfiguration whenever you trigger it. This is almost similar to nConfig where it will be directly reconfigure the FPGA
  • YSaka7's avatar
    YSaka7
    Icon for New Contributor rankNew Contributor
    7 years ago

    Thank you for your reply.

    Sorry, I was wrong.

    I made a mistake in writing step1.

    A correct question is as follows.

    ---

    I want to reconfiguration MAX10(10M08DAU324I7G) FPGA with selecting configuration image0/1.

    step1. Write register of IP Core Avalon-MM Address Map Offset:1 Bit:1=config image0or1 Bit:0=1(trigger)

    step2. Wait busy signal de-asserted.

    step3. ReConfiguration start.

    When busy signal never de-assert, I want to abort process step2.

    Please teach me maximum time (or clock cycle) of write register to busy signal de-asserted.

    ---

    It writes in the datasheet(Intel MAX10 FPGA Configuration User Guide Table34.) so.

    The busy signal is generated right after the write cycle, while the configuration

    image information is registered. Once busy signal is high, writing to this address

    is ignored until the process is completed and the busy signal is de-asserted.

    I think I have to wait busy signal de-asserted after set config_sel before set trigger reconfiguration.