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New Contributor

7 years ago

Question about MAX10 FPGA's specification on using Altera Dual Configuration IP Core.

I want to reconfiguration MAX10(10M08DAU324I7G) FPGA with selecting configuration image0/1. step1. Write register of IP Core Avalon-MM Address Map Offset:0 Bit:1=config image0/1 Bit:0=1(trigger) st...

JohnT_Altera

Regular Contributor

7 years ago

Yes, your understanding is correct. If you only performed config_sel then yes, you will need to wait for busy signal to be de-asserted before triggering reconfiguration.

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Question about MAX10 FPGA's specification on using Altera Dual Configuration IP Core.

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